Head of Hardware Engineering

Taglynk · India

About the Company

Our client is a leading quantum security company building the cryptographic backbone for a post-quantum world. Their portfolio spans Quantum Key Distribution (Armos QKDN terrestrial fibre, free-space, and satellite), Quantum Random Number Generation (Tropos discrete and CV-QRNG SiP), Post-Quantum Cryptography (HODOS), and emerging quantum sensing platforms. They work with national agencies and global commercial partners and have deployed a pioneer 1000 km QKD network.

The Role

We are looking for a hands-on technical leader to own the entire hardware engineering function—high-speed digital, analog/mixed-signal, FPGA, PCB, and full system integration through to ruggedised, manufacturable products. You will be the single point of accountability for the hardware roadmap across every product line.

A quantum or photonics background is not required; that domain knowledge sits with the physics and product teams. What is required is a world-class electronics leader who can architect and ship complex mixed-signal / FPGA-heavy products at production scale.

This is a critical, end-to-end ownership role. You will set technical direction, build and mentor the team, drive design-for-manufacturing and qualification, and represent the hardware portfolio to government and enterprise customers.

What You Will Own

• Full hardware lifecycle: Requirements capture, architecture, schematic and PCB design, FPGA RTL and verification, bring-up, characterisation, EVT/DVT/PVT, qualification, and volume manufacturing transfer.
• FPGA and digital subsystems: Partition and architect Zynq UltraScale+ MPSoC and Versal-class designs; lead high-speed SerDes (JESD204C), DSP pipelines (DSP48E2), and embedded Linux/PetaLinux integration for QKD and QRNG signal processing.
• Analog and mixed-signal frontends: Low-noise amplifier design, high-speed Gsps-class ADC/DAC interfacing, precision clocking and timing distribution, low-jitter PLL architectures, high-resolution data acquisition, and the full sensor-to-digital signal chain.
• PCB and system integration: High-speed digital and mixed-signal stack-ups, signal/power integrity, EMI/EMC compliance, and ruggedised industrial and defence-grade enclosures.
• Team leadership: Build, structure, and mentor a hardware engineering team of 15+ across digital, analog, FPGA, and layout disciplines. Set engineering standards, design reviews, and quality gates.
• Customer and partner engagement: Represent company hardware to defence forces and international partners; translate field requirements into product specifications.
• Manufacturing and supply chain: Own DFM/DFT/DFA, supplier qualification, component obsolescence strategy, and the path from prototype to volume production.
• IP and standards: Drive patent generation, contribute to ETSI/ITU/IEEE quantum security standards, and ensure compliance with FIPS, Common Criteria, and applicable defence qualification standards.

What You Bring

• Experience: 15+ years in hardware engineering with at least 5 years leading multidisciplinary teams. Demonstrated track record of taking complex hardware products from concept to volume production.
• Core Technical Depth:
• High-speed digital design: Multi-Gbps interface design, DDR4/DDR5, PCIe Gen3/Gen4/Gen5, 10/25/100G Ethernet, SerDes channel design and equalisation, signal- and power-integrity simulation (HyperLynx, ADS, HFSS, Sigrity), SoC integration, embedded Linux/PetaLinux, secure boot, and root-of-trust architectures.
• FPGA: Xilinx/AMD Zynq UltraScale+ and Versal, Vivado, MPSoC architecture and partitioning, AXI interconnect, high-speed SerDes (GTH/GTY/GTM), JESD204B/C, DSP pipelines, RTL coding (SystemVerilog/VHDL), constrained-random verification (UVM), simulation, and timing closure on demanding designs.
• Analog/mixed-signal: Low-noise amplifier design, high-speed ADC/DAC interfacing, precision timing and clock distribution, low-jitter PLLs, low-noise power-supply design for noise-sensitive instrumentation, and the analog-digital boundary on mixed-signal boards.

Preferred Experience:

• Telecom or networking hardware (line cards, optical transport, switching/routing platforms, NPUs).
• Test and measurement instrumentation, SDR platforms, or high-precision data acquisition systems.
• ASIC, SiP, or chiplet development.
• Defence, aerospace, or space-qualified hardware (MIL-STD, JSS, ECSS) and engagement with the defence ecosystem.
• Cryptographic / security hardware (HSMs, FIPS 140-2/3, Common Criteria EAL4+).
• Education: M.Tech, M.S., or PhD in Electronics, Electrical, or Computer Engineering from top-tier institutions, or equivalent industry track record.
• Leadership Traits: Strong systems thinking, calm under technical pressure, decisive in architectural trade-offs, comfortable in the lab as well as the boardroom, and able to attract and grow talent.